Verilog is a hardware description language (HDL) used to model electronic systems.
The language (sometimes called Verilog HDL) supports the design, verification, and implementation of analog, digital, and mixed-signal circuits at various levels of abstraction.
The designers of Verilog wanted a language with syntax similar to the C programming language so that it would be familiar to engineers and readily accepted.
The language is case-sensitive, has a preprocessor like C, and the major control flow keywords, such as "if" and "while", are similar.
The formatting mechanism in the printing routines and language operators and their precedence are also similar.
The language differs in some fundamental ways.
Verilog uses Begin/End instead of curly braces to define a block of code.
The definition of constants in Verilog require a bit width along with their base, consequently these differ.
Verilog 95 and 2001 don't have structures, pointers, or recursive subroutines, however SystemVerilog now includes these capabilities.
Finally, the concept of time —so important to a HDL— won't be found in C.
Source: Wikipedia (http://en.wikipedia.org/wiki/Verilog)