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µC/FS is a file system for embedded applications.
µC/FS is a file system for embedded applications.
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Mentor Graphics - IC Design.


SHARC Processor Evaluation Kit Limited Time Offer
Analog Devices is offering a 50% discount on new SHARC Processor Family evaluation kits until July 31, 2008. The SHARC Processor fits into a variety of applications such as Digital Home, Pro Audio, Industrial and Instrumentation, Automotive, Military, and Medical. The following kits will be discounted to $249 through your local Distributor: ADZS-21262-EZLITE, ADZS-21364-EZLITE, ADZS-21369-EZLITE, and ADZS-21375-EZLITE.
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Registration Open for Mentor Graphics U2U 2008!
Learn, Share and Network with hundreds of your peers at User2User 2008, the Mentor Graphics International User Conference. Register early and be one of the first to sign-up for FREE Product Training Classes while space is available! Register by October 5 for Early Bird Pricing of $500! When: November 5-6, 2008; Product Training Classes on November 4 Where: Santa Clara Marriott, Santa Clara, CA Learn Technical Product...
Click here to preview in another window preview: http://www.mentor.com   date: 7/18/2008

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Cadence Expands System-Level Offerings with Introduction of C-to-Silicon Compiler
Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, today introduced Cadence® C-to-Silicon Compiler, a high-level synthesis product that improves designer productivity up to 10 times in creating and re-using system-on-chip IP. The innovative technology in C-to-Silicon Compiler helps bridge the gap between register transfer level (RTL) models commonly used to verify, implement, and integrate...
Click here to preview in another window preview: http://www.cadence.com   date: 7/16/2008

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Cambridge Consultants XAP5 core sets new standard for 16-bit processors
Cambridge Consultants has launched its next generation XAP processor core - XAP5 – offering wireless and sensor chip designers an advanced level of 16-bit processing performance combined with low energy consumption and efficient use of low cost memory, making it ideally suited for cost-sensitive high-volume products. XAP5 combines the economy of a 16-bit data word with a 24-bit address space for large programs up to 16 Mbytes, which suits...
Click here to preview in another window preview: http://www.cambridgeconsultants.com   date: 7/16/2008

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AWR Enhances Visual System Simulator™ Software - Version 2008 …
AWR®, the innovation leader in high-frequency electronic design automation (EDA), today announced Version 2008 of its Visual System Simulator (VSS) software suite for the end-to-end design and optimization of communications systems. The latest release of VSS significantly enhances the flexibility for users while adding many new features and capabilities.
Click here to preview in another window preview: http://web.awrcorp.com   date: 7/15/2008

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Sonics Eliminates Barriers To Multichannel Memory Management Industry Adoption With New Interleav…
Sonics Inc., a premier supplier of system-on-chip SMART Interconnect solutions, today announced the availability of Interleaved Multichannel Technology (IMT), a breakthrough in SoC architecture that eliminates the challenges associated with transitioning to multichannel memory management for achieving high memory access performance
Click here to preview in another window preview: http://www.sonicsinc.com   date: 7/10/2008

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New SonicsSX SMART Interconnect Solution Solves Memory Performance Problem for High …
Sonics Inc, a premier supplier of system-on-chip SMART Interconnect solutions, today announced the availability of the SonicsSX SMART Interconnect solution. Designed for SoCs requiring high quality, high definition, or HQHD, video support, SonicsSX accelerates video performance and eases global integration of intellectual property cores and subsystems onto a single chip. SonicsSX also contains a new Interleaved Multichannel Technology (IMT)...
Click here to preview in another window preview: http://www.sonicsinc.com   date: 7/10/2008

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eSOL’s Multi-core ready RTOS


eSOL’s Multi-core ready RTOS. The eT-Kernel Multi-Core Edition supports two scheduling modes, True SMP Mode (TSM) and Single Processor Mode (SPM). Both provide software developers with a blended multiprocessor RTOS, and the scalability and high throughput efficiency of SMP, with the more deterministic and realtime characteristics of AMP. All this is within a single tightly-coupled multiprocessor solution supporting POSIX 1003.1. 2004.
eSOL’s Multi-core ready RTOS


 

 

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