 
SHARC Processor Evaluation Kit Limited Time Offer
Analog Devices is offering a 50% discount on new SHARC Processor Family evaluation kits until July 31, 2008.
The SHARC Processor fits into a variety of applications such as Digital Home, Pro Audio, Industrial and Instrumentation, Automotive, Military, and Medical.
The following kits will be discounted to $249 through your local Distributor: ADZS-21262-EZLITE, ADZS-21364-EZLITE, ADZS-21369-EZLITE, and ADZS-21375-EZLITE.
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Aldec Downloads - Demos, White Papers, Tutorials
SystemC-Primer 1.1. HDL / VHDL Tutorials.
Evita-VHDL interactive primer.
ATP-Verilog 4.6 - Advanced Testing Package Tool.
ATP-VHDL 4.6. Advanced Testing Package Tool, designed to test an engineer's competency with the VHDL langauge.
Riviera 2007.06 - Powerful, high performance ASIC and High Density FPGA verification environment.
Active-HDL 7.2sp2 - Completely integrated FPGA design entry and verification environment for VHDL, Verilog,...
preview:
http://www.aldec.com
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demo
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SystemC OCP Models
SystemC OCP 2.1 Models for Transaction Layer 1 (TL1) and Transaction Layer 2 (TL2) are available to OCP-IP Members and the general public.
If you belong to a member company, please enter the Members Only site to download the SystemC models.
The models are freely available to non-members for research use; just read the 'click through' Research License Agreement and fill out the information requested.
Once this is complete, you will receive...
preview:
http://www.ocpip.org
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With PADS® I/O Designer, you can easily create legal FPGA pin assignments—up to 50% times faster—with its correct-by-construction, drag and drop functionality.
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I/O Designer follows major FPGA vendor rules for correct I/O assignments.
It also eliminates re-spin risk, improves PCB performance, and reduces routing congestion.
View the free demo.
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