login to eCLIPS or find out about eCLIPS
eSOL’s Multi-core ready RTOS
Blended multi-processing combines the benefits of AMP and SMP
home - www.eg3.com
 
NanoSSH: Embedded SSH Client and Server
home > fpga > cores > projects, webinars
Mentor Graphics - IC Design.


SHARC Processor Evaluation Kit Limited Time Offer
Analog Devices is offering a 50% discount on new SHARC Processor Family evaluation kits until July 31, 2008. The SHARC Processor fits into a variety of applications such as Digital Home, Pro Audio, Industrial and Instrumentation, Automotive, Military, and Medical. The following kits will be discounted to $249 through your local Distributor: ADZS-21262-EZLITE, ADZS-21364-EZLITE, ADZS-21369-EZLITE, and ADZS-21375-EZLITE.
.

 

 

project   1-5 star rating for this site   site recommendation - wow, cool, new
FPGA CPU / last update 2003
The purpose of this site is to share the lore of designing custom processors and integrated systems-on-chips using FPGAs (field-programmable gate arrays). The XSOC Project - an unsupported collection of experimental hardware and software designs and specifications, cited in the Circuit Cellar magazine series, "Building a RISC System in an FPGA", and providing an example for the noble purpose of teaching computer design.
Click here to preview in another window preview: http://www.fpgacpu.org   date: 2/5/2003

.

project   1-5 star rating for this site  
OpenCores
OpenCores is a loose collection of people who are interested in developing hardware, with a similar ethos to the free software movement. Currently the emphasis is on digital modules called 'cores', since FPGAs have reduced the incremental cost of a core to approximately zero.
Click here to preview in another window preview: http://www.opencores.org  

webinar   1-5 star rating for this site  
Optimize for Performance or Power with Tensilica and Virage Logic Core-Optimized IP Kits
Join Virage Logic and Tensilica for an informative technical webinar on the recently introduced Core-Optimized IP Kits for Tensilica's Diamond Standard processor family. Specifically tuned to optimize the performance of Tensilica's Diamond Standard product line processor cores, this joint collaboration provides mutual customers with physical IP that leverages Virage Logic's silicon proven embedded memory IP and standard cell libraries to...
Click here to preview in another window preview: http://www.techonline.com   date: 1/24/2007

webinar   1-5 star rating for this site  
Using Soft Cores to Avoid Microprocessor Obsolescence
You may have a legacy design that is still in production and is manufactured with components, including microprocessors, that are being end-of-life'd by the supplier. Or you may have a legacy design that you want to cost reduce, and integrate the processor with surrounding peripherals without incurring the high NRE cost of ASIC development. Microprocessors used in these situations are often venerable 8 or 16 bit architectures like the 8051,...
Click here to preview in another window preview: http://www.latticesemi.com   date: 10/17/2007

eSOL’s Multi-core ready RTOS


eSOL’s Multi-core ready RTOS. The eT-Kernel Multi-Core Edition supports two scheduling modes, True SMP Mode (TSM) and Single Processor Mode (SPM). Both provide software developers with a blended multiprocessor RTOS, and the scalability and high throughput efficiency of SMP, with the more deterministic and realtime characteristics of AMP. All this is within a single tightly-coupled multiprocessor solution supporting POSIX 1003.1. 2004.
eSOL’s Multi-core ready RTOS


 

 

eg3.com 'meta' info - site map, keywords, how to contact us . . .