login to eCLIPS or find out about eCLIPS
Industry standard COM Express CPU module and dual XMC  modules
Industry standard COM Express CPU module and dual XMC modules
home - www.eg3.com
 
Arium Emulators are the Core of Intel Atom Development!
home > dsp > filters > papers, showcase
Mentor Graphics.

Free News Alerts by Keyword
Interested in embedded technology? Are you an engineer or designer? e-clips helps you follow the latest news on key topics like multicore, FPGAs, 8051, ESL, PC/104 and more!
Free News Alerts by Keyword

 

 

paper   1-5 star rating for this site  
A Method for Designing Low-Pass FIR Digital Filters
A class of finite-impulse-response (FIR) digital filters has been developed to perform certain frequency-limiting, decimation, and differentiation (with respect to time) functions on a time series of data samples. The method is implemented by use of design equations that contain parameters that can be adjusted to obtain the desired functionality while limiting such undesired effects as aliasing and gain ripple. The original application is...
Click here to preview in another window preview: http://www.nasatech.com   date: 3/1/2000 |

paper   1-5 star rating for this site  
Design of a FIR filter using a FPGA
A modification of the filter design described in Arcetri Technical Report N 5/2002 is presented. The overall structure is similar, but the the digital local oscillator is moved after the first filter and after the frequency decimation. With this modification the design proposed here presents some advantage in terms of gate usage and spectral dynamic range.
Click here to preview in another window preview: http://www.arcetri.astro.it   date: 3/1/2003 |

paper   1-5 star rating for this site  
Digital Filtering Alternatives for Embedded Designs
Whether it’s filtering out 60 Hz noise sources or looking for a signature in a certain frequency band, signal processing and filtering applications are abundant and easier than ever to implement with the right tools. How does the embedded micro-controller designer decide the best path to take when tackling his filtering problem (with the least amount of pain)? This paper will provide the necessary guidance to select the best approach for a...
Click here to preview in another window preview: http://www.quickfiltertech.com   date: 9/2/2006 |

  Featured Products:

Innovative Integration - DSP Products
Innovative Integration provides board-level hardware products that integrate the best analog I/O and reconfigurable FPGAs ... Click for details!

Introducing EngineerZone, where
A new online technical support forum by Analog Devices providing direct access to DSP support engineers. Search FAQs and ... Click for details!


paper   1-5 star rating for this site  
FIR Filter Fits in an FPGA using a Bit Serial Approach
In this paper, I have shown that it is possible to pack a relatively complex digital signal processing function into an FPGA by using bit serial structures. The cost of bit serial architectures in terms of more clock cycles can be offset to some degree by the shorter delay paths between pipeline registers. The resulting design is fast enough for many applications where a bit serial process may not have been considered.
Click here to preview in another window preview: http://www.andraka.com   |

showcase   1-5 star rating for this site  
Innovative Integration - DSP Products
Innovative Integration provides board-level hardware products that integrate the best analog I/O and reconfigurable FPGAs to provide cost-effective solutions for challenging data acquisition and signal processing applications.
Click here to preview in another window preview: http://www.innovative-dsp.com   ULCLOGO |

showcase   1-5 star rating for this site  
PSK Demodulator for Wireless Communications Receivers
Phase-shift keying (PSK) demodulator is widely used in modern wireless communication receivers for waveform phase demodulation and symbol recovery. Innovative Integration (II) has developed a small footprint (<10% with Xilinx Vertex5 SX95T) PSK demodulation system that performs high speed BPSK, QPSK, and 8PSK demodulation with symbol rate up to 1.4MSPS. Together with II digital radio receiver (DRR) providing powerful channelization technique, the II-PSK-demod core can be flexibly customized as multi-channel parallel demodulation systems or as a high speed single channel broad band demodulator. With Xilinx System Generator, the design of Digital Down Converter (DDC) and the demodulation system can be rapidly prototyped and simulated in MATLAB/Simulink environment. II MATLAB/Simulink board support package (BSP) allows designers to implement a mature DSP core on X5 series board within hours, which helps to accelerate the development life cycle.
Click here to preview in another window preview: http://www.innovative-dsp.com   ULCLOGO |

showcase   1-5 star rating for this site  
Introducing EngineerZone, where DSP engineers go for answers
A new online technical support forum by Analog Devices providing direct access to DSP support engineers. Search FAQs and share knowledge with DSP developers and peers. Join us www.analog.com/EZ
Click here to preview in another window preview: http://ad.doubleclick.net   |

Mentor Graphics
.
 

 

eg3.com 'meta' info - site map, keywords, how to contact us . . .