 
Introducing the FireCracker!
Based on Analog Devices popular
Blackfin
embedded processor, Silica has developed the FireCracker Development and Reference Design Platform for audio and video applications.
FireCracker is a unique concept of a hybrid between a development board and a reference design that enables design engineers to bring embedded computing solutions from concept to production in record time.
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paper
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A Method for Designing Low-Pass FIR Digital Filters
A class of finite-impulse-response (FIR) digital filters has been developed to perform certain frequency-limiting, decimation, and differentiation (with respect to time) functions on a time series of data samples.
The method is implemented by use of design equations that contain parameters that can be adjusted to obtain the desired functionality while limiting such undesired effects as aliasing and gain ripple.
The original application is...
preview:
http://www.nasatech.com
date: 3/1/2000
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paper
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Design of a FIR filter using a FPGA
A modification of the filter design described in Arcetri Technical Report N 5/2002 is presented.
The overall structure is similar, but the the digital local oscillator is moved after the first filter and after the frequency decimation.
With this modification the design proposed here presents some advantage in terms of gate usage and spectral dynamic range.
preview:
http://www.arcetri.astro.it
date: 3/1/2003
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paper
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Digital Filtering Alternatives for Embedded Designs
Whether it’s filtering out 60 Hz noise sources or looking for a signature in a certain frequency band, signal processing and filtering applications are abundant and easier than ever to implement with the right tools.
How does the embedded micro-controller designer decide the best path to take when tackling his filtering problem (with the least amount of pain)? This paper will provide the necessary guidance to select the best approach for a...
preview:
http://www.quickfiltertech.com
date: 9/2/2006
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paper
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FIR Filter Fits in an FPGA using a Bit Serial Approach
In this paper, I have shown that it is possible to pack a relatively complex digital signal processing function into an FPGA by using bit serial structures.
The cost of bit serial architectures in terms of more clock cycles can be offset to some degree by the shorter delay paths between pipeline registers.
The resulting design is fast enough for many applications where a bit serial process may not have been considered.
preview:
http://www.andraka.com
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