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Integrated RTOS, communications stacks and middleware
Integrated RTOS, communications stacks and middleware
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Mentor Graphics - IC Design.


SHARC Processor Evaluation Kit Limited Time Offer
Analog Devices is offering a 50% discount on new SHARC Processor Family evaluation kits until July 31, 2008. The SHARC Processor fits into a variety of applications such as Digital Home, Pro Audio, Industrial and Instrumentation, Automotive, Military, and Medical. The following kits will be discounted to $249 through your local Distributor: ADZS-21262-EZLITE, ADZS-21364-EZLITE, ADZS-21369-EZLITE, and ADZS-21375-EZLITE.
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Cadence (EDA) Webinar Archive
Cadence is a leading vendor in the EDA space. This is their archive of webinars on topics as varied as verification, EDA, SystemVerilog, Verification, PCB design and more.
Click here to preview in another window preview: http://www.cadence.com  

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Cadence White Papers
White papers with topics in Functional verification, Digital IC design, Custom IC design, Design for manufacturing, and Silicon-package-board co-design.
Click here to preview in another window preview: http://www.cadence.com  

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Technical Papers from Synopsys
Topics such as: * Measuring and Improving IC Design Productivity * A Practical Methodology for Calculating IR Drop Targets for Advanced Designs * Power Integrity for SoCs: Power Planning and Signoff Flows * Implementing Next-Generation Radiation-Hardened ASICs * Design Practices and Strategies for Efficient Signal Integrity Closure * Power Management In Complex SoC Design * Hierarchical Design Techniques * etc.
Click here to preview in another window preview: http://www.synopsys.com  

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Council on Electronic Design Automation (CEDA)
The objectives of IEEE/CEDA include fostering design automation of electronic circuits and systems at all levels, by means of publications, conferences/workshops and volunteer activities.
Click here to preview in another window preview: http://www.c-eda.org  

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European Electronic Chips & Systems Design Initiative (ECSI)
ECSI was established in 1993 with support of European Commission via the ESPRIT project ECIP and sponsoring of participating companies, and is open to all institutions or industries who wish to support EDA standardization in Europe.
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MUG - Mentor Graphics Users Group
MUG, the International Mentor Graphics Users' Group, was formed in 1983. Its purpose is to provide users of Mentor Graphics products and/or services with: A means for the exchange of technical, administrative, and management information pertaining to the use of these products and/or services; Peer access with fellow users, networking, and camaraderie Communication and liaison with Mentor Graphics on equipment
Click here to preview in another window preview: http://www.mugweb.org  

eSOL’s Multi-core ready RTOS


eSOL’s Multi-core ready RTOS. The eT-Kernel Multi-Core Edition supports two scheduling modes, True SMP Mode (TSM) and Single Processor Mode (SPM). Both provide software developers with a blended multiprocessor RTOS, and the scalability and high throughput efficiency of SMP, with the more deterministic and realtime characteristics of AMP. All this is within a single tightly-coupled multiprocessor solution supporting POSIX 1003.1. 2004.
eSOL’s Multi-core ready RTOS


 

 

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