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overview    

Boundary-Scan Tutorial
Since its introduction as an industry standard in 1990, boundary-scan (also known as JTAG) has enjoyed growing popularity for board level manufacturing test applications. Boundary-scan has rapidly become the technology of choice for building reliable high technology electronic products with a high degree of testability. Due to the low-cost and IC level access capabilities of boundary-scan, its use has expanded beyond traditional board test...
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Built-in self-test (BIST) @ Wikipedia
A built-in self-test (BIST) mechanism within an integrated circuit (IC) is a function that verifies all or a portion of the internal functionality of the IC. For example, a BIST mechanism is provided in advanced fieldbus systems to verify functionality. At a high level this can be viewed similar to the PC BIOS's Power-On Self-Test (POST) that performs a self-test of the RAM and buses on power-up.Alternative definition can be Built-in Self...
preview: http://en.wikipedia.org   |

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Design For Test @ Wikipedia
Design for Test (aka 'Design for Testability' or 'DFT') is a name for design techniques that add certain testability features to a microelectronic hardware product design. The premise of the added features is that they make it easier to develop and apply manufacturing tests for the designed hardware. The purpose of manufacturing tests is to validate that the product hardware contains no defects that could adversely affect the product’s...
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Joint Test Action Group (JTAG) @ Wikipedia
Joint Test Action Group (JTAG) is the usual name used for the IEEE 1149.1 standard entitled Standard Test Access Port and Boundary-Scan Architecture for test access ports used for testing printed circuit boards using boundary scan. JTAG was an industry group formed in 1985 to develop a method to test populated circuit boards after manufacture. At the time, multi-layer boards and non-lead-frame ICs were becoming standard and making...
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Calibre nmDRC
Total cycle time is on the rise due to more complex and larger designs, higher error counts and more verification iterations. Calibre® nmDRC responds to the need for reduced cycle time with revolutionary new capabilities that differentiate Calibre nmDRC substantially from traditional DRC tools including dynamic results visualization, equation-based DRC, direct database access and integrated DFM analysis.
preview: http://www.mentor.com   |

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Calibre nmOPC
The Calibre nmOPC tool offers best-in-class accuracy, speed, and cost of ownership. Like all Calibre family products, Calibre nmOPC runs on the fully integrated Calibre hierarchical geometry engine uniquely enabling a fully integrated design to mask flow with a unified command language. Calibre nmOPC also supports the OASIS output format to minimize output file size. Streamlined hierarchical processing algorithm in Calibre nmOPC enables the tool to take advantage of natural design hierarchy to improve turn around time, computational efficiency, and throughput compared to flat processing tools.
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Tessent
The Mentor Graphics Tessent™ product suite provides comprehensive silicon test and yield analysis solutions that address the challenges of manufacturing test, debug, and yield ramp for today’s SoCs. Built on the foundation of the best-in-class solutions for each test discipline, Tessent brings them together in a powerful test flow that ensures total chip coverage.
preview: http://www.mentor.com   |