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Mentor Graphics
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webinar
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Best Practices for Quick Closure of Verilog Designs
When you design ASIC you have to deal with the tangled reset circuits, multiple clock domains, power dissipation, and other complex issues.
In this presentation we will discuss the best design practices for the proper reset circuit, avoiding glitches in cross domain data paths, special consideration for using gated clocks in your design, and some coding techniques for the most efficient verification of the design.
Following these practices...
preview:
http://www.aldec.com
date: 8/14/2008
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webinar
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Cut Months and Millions from ASIC Design
Learn about a unique system development method that can dramatically reduce your ASIC-based system design’s time-to-market and total cost.
In this 20-minute webcast, you’ll see how Altera’s ASIC development system provides: In-system, at-speed verification of both hardware and software The lowest risk approach to custom
preview:
http://www.altera.com
date: 7/11/2008
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webinar
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Implementing Large and Complex 65-nm ASICs in the Magma Flow
65-nanometer process technology advancements allow us to put more functionality into a single large, complex chip.
As we pack hundreds of millions of transistors into a chip, increased EDA tool performance and integrated design flows are necessary to address all nanometer issues and effects.
In this webinar, Fastrack Design describes the implementation of a high-performance, 65-nm ASIC using the Magma flow.
Synthesis, virtual prototyping,...
preview:
http://www.magma-da.com
date: 11/27/2007
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webinar
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Verification of Complex Analog Designs
Analog IC designers face increasing challenges in the design and verification of analog blocks and intellectual property.
The fact that standards are getting ever more stringent is imposing tighter specifications on analog blocks.
These blocks are now larger, include more functionality, operate at higher frequency and are more susceptible to noise and crosstalk from neighboring digital blocks.
Even more challenges emerge as analog designs...
preview:
http://www.techonline.com
date: 6/19/2007
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webinar
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Verification of Next-Generation Mixed-Signal Communication SoC In 65/45nm Technologies
Next-generation solutions for today's integrated communications applications combine analog/mixed signal circuit methodology with ASIC design flows based on advanced 65/45nm process technologies.
The designs provide better performance and complex functionality for a consumer market that demands integrated solutions for voice, data and video.
In mixed-signal systems such as these, the interaction between digital and analog blocks must be...
preview:
http://www.techonline.com
date: 6/21/2007
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Data Device Corporation (DDC) is recognized as a leading international supplier of high-reliability data interface products for military and commercial aerospace applications for over 40 years and MIL-STD-1553 products for more than 25 years.
DDC’s product lines consist of advanced data bus technology for high-speed Ethernet and Fibre Channel networks, MIL-STD-1553 and ARINC 429 data bus boards and components, synchro/resolver technologies, and solid-state power controllers and motor drives.
Product forms include ASICs, Components, and PCI, PMC, cPCI, PC/104, PC/104 Plus, PCMCIA, PC, VME, VXI, USB, and PCIe cards.
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